Following the development of integrated circuit (IC) technology, the packing requirement is more and more strict for the ICs. Nowadays, a ball grid package (BGA) technology is widely applied in most high pin-count chips such as graphic chips, chip modules and so forth. The BGA packaging substrate is classified to five types: a plastic BGA (PBGA) substrate, a ceramic BGA (CBGA) substrate, a flip-chip BGA (FCBGA) substrate, a tape BGA (TBGA) substrate, and a cavity-down PBGA (CDPBGA) substrate. An IC chip is electrically connected to the pad on the substrate via a connecting wire. Since the connecting wire is made of gold, so the pad is necessary to be coated with gold, for enhancing the connection between the connecting wire and the pad and for increasing the yield of the wiring process.
Reference is made to FIGS. 1A to 1G, which depict cross-sectional diagrams of the process flow in accordance with a selectively gold plating method of a PBGA substrate in the prior art. First of all, as shown in FIG. 1A, a laminated circuit board 100 is provided. It is understood that, the laminated circuit board 100 has not been coated with a solder mask layer, and the laminated circuit board 100 has a top surface 102 and a bottom surface 104 opposite to the top surface 102, wherein the laminated circuit board 100 has at least a through hole 100a therein. Next, as shown in FIG. 1B, the laminated circuit board 100 is subjected to panel plating for forming an electroplated layer 110 thereon, wherein the electroplated layer 110 comprises a first electroplated layer 112 located on the top surface 102, a second electroplated layer 114 located on the bottom surface 104, and a third electroplated layer 116 located in the through hole 100a, and wherein the first electroplated layer 112, the second electroplated layer 114 and the third electroplated layer 116 electrically connect to one another. And then, as shown in FIG. 1C, a first photolithography/etching step is performed, for patterning the first electroplated layer 112 to form a circuit pattern 112a and a pad 112b. Subsequently, as shown in FIG. 1D, an electroplating resist pattern 120 is partially formed on the top surface 102 and the bottom surface 104 to expose the pad 112b located on the top surface 102 and an area of the second electroplated layer 114 that needs to be subsequently electroplated with a protective layer. It is understood that a photolithography step is employed in the step of forming the electroplating resist pattern 120. And then, an electroplating step is performed, for electroplating a protective layer such as a nickel/gold layer 130a on the area of the second electroplated layer 114 that is uncovered with the electroplating resist pattern 120, so as to protect the area of the second electroplated layer 114 from being oxidized. At this moment, the third electroplated layer 116 in the through hole 100a is employed to electrically connect the pad 112b on the top surface 102, so that the current required for electroplating the pad 112b on the top surface 102 is transmitted from the second electroplated layer 114 of the bottom surface 104 via the through hole 100a to the top surface 102, thereby simultaneously electroplating a nickel/gold layer 130b on the pad 112b on the top surface. Thus, the required nickel/gold layer 130a and the nickel/gold layer 130b are simultaneously electroplated on top surface 102 and the bottom surface 104, as shown in FIG. 1D. Consequently, the electroplating resist pattern 120 is removed, as shown in FIG. 1E. Next, a second photolithography/etching step is performed, for patterning the second electroplated layer 114 to form a circuit pattern 114a and a pad 114b. It can be understood that, during the second photolithography/etching step, a required photoresist pattern 140 is formed on the top surface 102 and the bottom surface 104, followed by etching the second electroplated layer 114 to define the circuit pattern 114a and the pad 114b, as shown in FIG. 1F. And then, the photoresist pattern 140 is removed. Afterward, as shown in FIG. 11G, a solder mask layer 150 is formed on the top surface 102 and the bottom surface 104, so as to complete the prior PBGA substrate that is subjected to selectively gold plating. During the selectively gold plating process in the prior art, the production of the PBGA substrate for carrying chips is necessarily subjected to at least twice of line photolithography/etching steps, resulting in higher production cost and lowering product yield due to many times of line photolithography/etching steps.
Another selectively gold plating process in the prior art is to dispose many plating bars on the PBGA substrate for electroplating the nickel/gold layer on the pads. However, so many plating bars occupy much of the area of the PBGA substrate, for decreasing the area for disposing wires. In addition, for applying the PBGA substrate in high frequency, it easily leads to occur the problem of noise caused by the antenna effect due to redundant plating bars.